This invention relates to a semiconductor apparatus, more particularly to a technology for easily and unfailingly running a conduction test thereof.
In the conduction test of a semiconductor apparatus, it is confirmed, prior to the test, neither disconnection nor short circuit has occurred in respective internal terminals.
In the configuration shown in FIG. 13, a numeral 001 denotes a semiconductor chip, a numeral 002 denotes an internal circuit integrated on the semiconductor chip 001, numerals 003–008 denote terminals for sending and receiving signals between the internal circuit 002 and an external system of the semiconductor chip 001. Numerals 009–014 denote diodes respectively connected to the terminals 003–008 and formed in the forward direction with respect to a power-supply potential (VDD) and in the reverse direction with respect to a ground potential (VSS). To the terminal 003, which is a test object, is applied a potential exceeding <power-supply potential (VDD)+threshold voltage Vt of diode 009>, and to the other terminals 004–008 is applied the ground potential (VSS). At the same time, the flow of a current at the terminal 003 is measured. When the current value is 0, the terminal 003 is not conducted. When an unusually excessive current is detected, there is a short circuit between the terminal 003 and any of the other terminals. These steps are implemented to each of all the terminals in the same manner.
Challenges are that the more increase in the number of the terminals, the longer hours and higher cost are required by the test because the test is to be run for each terminal; and that the test requires a relatively expensive test device capable of measuring a current at the time of applying a voltage.
FIG. 14 shows a configuration of mounting a plurality of semiconductor chips in a package, in which a numeral 101 denotes a parent chip and a numeral 115 denotes a child chip superposed on the parent chip 101. The function of an internal circuit 116 of the child chip 115 is tested via an internal circuit 102 by controlling and observing the terminals 103–108 on the parent chip 101 from outside of the package. In doing so, a conduction test is indirectly run to chip-connecting terminals 117–120 and 125–128 and wires 133–136. The problem in that is there arises the necessity to take into account how the chip-connecting terminals should be combined in order to run the test to detect all of possible disconnections and short circuits therein, which requires a great deal of ingenuity in creating a test pattern to be supplied to the parent chip.